The present invention relates generally to metal Schottky junction field effect transistors (MESFET) and more specifically to an isolated top gate MESFET and a method of making and trimming or altering its voltage characteristics.
MESFETs are junction field effect transistors in which at least one gate is formed by use of a Schottky barrier diode rather than by an PN junction diode. The performance of such devices can be improved when they are built such that the two gates are isolated from one another. This is particularly valuable in integrated circuit applications where one of the gates only weakly modulates the channel and has significant junction leakage and/or capacitance associated therewith. The weak, parasitic loaded gate may be connected to a non-sensitive circuit node, often the source, while the other gate is used as a device control gate thereby reducing the parasitics on the control gate.
Another advantage afforded by an isolated gate structure is that several devices can be built in a common bottom gate isolated island rather than in separate isolated islands. This saves die area and improves match of matched pairs by allowing the members of the pair to be closer to one another.
Isolated gate devices can also be used as four terminal devices in which the second gate is the fourth terminal. Such devices permit novel circuit implementations not possible with a three terminal device. An example is use of the second gate to apply an automatic gain control signal to a field effect transistor being used as an amplifier device.
Several prior art methods which form isolated top gate devices are known. One uses an insulator or semi-insulating support region under the channel to eliminate the second junction thereby transforming the bottom gate into an MOS gate. Another method uses a closed geometry top gate in which the top gate encloses at least one of the source and drain contact regions. The enclosed region or regions is then connected by a second level of interconnect. These methods are difficult and expensive to produce, thus there is a need for improved methods.
For PN junction field effect transistors having thin channel regions and top gate ohmic contact regions, special processing must be produced to provide an appropriate top gate on the contact region isolation as illustrated in U.S. Pat. Nos. 4,456,918 and 4,495,694 to Beasom.
In MESFETs having a rectangular Schottky barrier diode top gate on the channel between two non-concentric source and drain regions, the designer must terminate the width of the top of the Schottky metal spaced from the edge of the channel in order to produce an isolated top gate. This separation is determined by the accuracy of forming the necessary apertures in the oxide such that it does not extend outside of the channel. The separation prevents the field effect transistor from being turned completely off and creates a parasitic field effect transistor having only a bottom gate which is in parallel with the main field effect transistor. Thus, although it creates an isolated top gate, it also produces a transistor which may not be applicable for all applications.
Prior art junction field effect transistors similar to the structure of FIG. 4 have not been designed for high voltage applications. The breakdown of the device is limited to the top gate to channel breakdown voltage which is within the 60 volt range. Thus there is a need for a design of a junction field effect transistor and more specifically a Schottky top gate junction field effect transistor which is capable of operating at higher voltages.
It is often desirable to adjust the characteristics of individual devices with respect to its own characteristics, or as compared to that of another device within the circuit. For example, operational amplifiers are typically designed with a differential amplifier for the input stage. The balance of the differential amplifier is dependent on component match. Processing variables prevent exact match from occurring. This mismatch appears as offset voltage and/or offset current. In some applications this offset voltage cannot be tolerated and must be adjusted or corrected. There are three basic prior art approaches, i.e.,
(1) offset adjustment by external potentiometer; PA1 (2) automatic offset correction by additional circuitry; and PA1 (3) offset adjustment by laster trimming of thin film resistors.
The external potentiometer approach uses a potentiometer external to the IC package to effect offset adjust. This approach has the disadvantage of requiring an additional component large in comparison to the IC package, thereby requiring extra board space and expense. The "automatic correction circuit" approach requires extensive additional circuitry which increases the chip area and overall cost. The laser trimming approach requires capital equipment investment by the manufacturer Also, the laser trimming must be performed prior to packaging.
One solution to these problems, as provided in U.S. Pat. No. 4,210,875 to Beasom, is to provide a junction field effect transistor having a plurality of parallel drain segments connected to a common drain terminal by fusible elements. By reversing biasing of the gate with respect to the reference terminal, a current flows through the fuse to disconnect the appropriate segment. This structure requires extra processing for the fuse, as well as only providing a digital or fixed number of adjustments. It does not provide an infinite number or analog style of adjustment. Thus, there exists a need for more finely tunable offset adjustment.
A further method known for adjusting the effective resistance of a resistor is to apply pulses to the resistor and therefore effectively trim by migration of the aluminum contact material into the resistive material between a plurality of special surface contacts along the length of the resistor thereby reducing its cross-sectional area. This is described in U.S. Pat. No. 4,606,781.
Therefore, it is an object of the present invention to provide a metal Schottky junction field effect transistor (MESFET) having an isolated top and bottom gate.
Another object of the present invention is to provide a MESFET having extended breakdown and improved output resistance.
A further object of the present invention is to provide an operational amplifier having an adjustable offset voltage capability wherein the adjustment is accomplished by applying voltages to external leads.
A still further object of the invention is to provide an operational amplifier with offset voltage adjustment capability requiring no special steps of manufacture or additional chip area.
A still even further object of the invention is to provide an operational amplifier wherein the offset voltage may be adjusted after packaging.
A still even further object of the present invention is to provide a method having minimum steps for forming complementary junction field effect transistors.
A still even further object of the present invention is to provide a junction field effect transistor which is capable of operating at higher voltages.
These and other objects are attained by forming a junction field effect transistor having a Schottky contact top gate which is isolated from the bottom gate. In one embodiment, the bottom gate region is formed as an annulus in the drain region, the source region is formed as an annulus in the bottom gate region and the top gate is formed as an annulus. Preferably, the top gate is concentrically interior the annular source region and a bottom gate contact is an annulus concentrically exterior to the source region. Drain contact is made exterior the annular bottom region. The low impurity concentration of the bottom gate and drain raise the breakdown voltage of the transistor.
A second drain region of a higher impurity concentration than the drain region is spaced from the interior of the aperture of the annular bottom gate. The second drain region reduces the on-resistance and when forming complementing junction field effect transistors, connects the channel to the drain.
The interior aperture of the annular bottom gate region may be formed sufficiently small such that a second junction field effect transistor is formed between the channel region and the drain region and controlled by the bottom gate region. This second junction field effect transistor has a high breakdown voltage and is in series with the first junction field effect transistor so as to extend the breakdown of the total device and improve its output resistance.
The top gate includes a field portion extending along the length of the channel and separated from the channel by an insulator of sufficient thickness so as to deplete the underlying channel region before the Schottky gate breakdown voltage is reached. This further raises the breakdown voltages of the transistor.
In a second embodiment, the source, drain and channel regions are formed as rectangular regions. The source, drain and bottom gate regions are covered by a field oxide except at the contact apertures and the channel region is covered by a thin insulator having a thickness less than the field insulator. As in the previous embodiment, the top gate region includes a portion extending substantially across the length of the channel region and is separated therefrom by the thin insulator to perform the same depletion function. In this embodiment the top gate may extend the entire width of the channel region and onto the field insulator such that the field effect transistor may be completely controlled or turned totally off. To assure that the Schottky top gate will completely control the width of the channel while maintaining isolation from the bottom gate, the top gate contact aperture is formed in the thin oxide and the field oxide prior to the formation of the channel region. Thus, the channel is self-aligned to the gate aperture. This assures that it is totally isolated from the bottom gate as well as completely controlling the resulting channel. In the alternative, it may stop short of the field oxide.
The voltage characteristics of a junction field effect transistor may be modified by forming the top gate as a Schottky gate and applyinq a plurality of current pulses through the top gate to the channel sufficiently to create electrically conductive areas between the top and bottom gates through the channel to reduce the effective width of the channel. The amount of channel width reduction is a function of the amplitude of the pulses. This provides an analog versus a digital trim or adjustment. The pulses are applied by biasing the top gate with respect to the source or drain region such that current flows from the gate through to the source or drain region in a direction opposite the normal current flow through the source or drain. This allows programming of the device from its external terminals.
To reduce the amount of programming current, the gate may be formed as two electrically parallel segments wherein the smaller of the two segments is used as the programming gate. A steering element, for example a resistor, is placed in series with the larger gate segment so that the current pulse as applied to the common input gate terminal is steered to the smaller gate segment. Alternatively, the source or drain, preferably the drain, is formed as two parallel segments. Programming is performed by providing a steering element to steer the current from a common gate through the smaller drain segment. The steering element device would be a diode connected in parallel series with the larger drain segment so as to allow flow in the normal operational versus the adjusting direction
The same principle may be used to adjust the voltage characteristics of a voltage following circuit which includes a pair of serially connected Schottky top gate junction field effect transistors. The steering circuit is provided such that the input terminal may be selectively biased with respect to a first or a second output terminal to provide current pulses to one of the two series connected transistors to adjust the voltage characteristic of that transistor from its gate through its channel.
The same principle may also be applied to differential amplifiers to adjust the offset. Steering devices are provided such that the series resistance of the differential amplifier is bypassed during program with the reversal of direction of current flow than that of the normal operation when the gate is biased relative to the common reference terminal.
Thus, it can be seen that with little or no modification to the circuits other than the steering element, the devices may be programmed using externally available terminals and thus, the process can be done at the final stage of manufacture, after packaging.
A method of forming the previously described MESFETs with a complementary PN junction field effect transistor is provided using only the steps required to form the PN junction field effect transistor. After the processing steps which form the source, drain and lower gate regions using common process steps, the two impurity introducing steps to form the channel and the top gate of the PN junction field effect transistor are performed. The first of these, the introduction of impurities to form the channel region connecting the source and drain in the PN junction field effect transistor, also forms an enhanced bottom gate region for the Schottky top gate junction field effect transistors. The next step which forms the top gate of the PN junction field effect transistor in the just-formed channel region, also forms the channel region of the complementary Schottky top gate junction field effect transistor. Thus, the steps used to form the PN junction field effect transistors, can also be used to form the Schottky top gate junction field effect transistors.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.